| Language of instruction : English |
| | | Exam contract: not possible |
|
Sequentiality
|
| |
|
No sequentiality
|
There is no data for this choice.
Change the language, year or choose another item in the dropdown list if it is available.
| Degree programme | | Study hours | Credits | P1 SBU | P1 SP | 2nd Chance Exam1 | Tolerance2 | Final grade3 | |
 | 3rd year Bachelor of Engineering Technology - Electronics and ICT Engineering Technology | Compulsory | 162 | 6,0 | 162 | 6,0 | Yes | Yes | Numerical |  |
|
| | | Learning outcomes |
- EC
| EC1 - The holder of the degree possesses general scientific and technological application-oriented knowledge of the basic concepts, structures and coherence of the specific domain. | | | - DC
| EA 1.5 The student knows the operation and function of the (advanced) functional building blocks for digital circuits. | | | | - BC
| The student knows the digital hardware, organization and architecture of modern computer architectures. | | | - DC
| EA -INF 1.1 The student knows the design principles and architectures to design and develop software in structured manner. | | | | - BC
| The student knows the concepts of instruction sets, assembly languages and how high level languages are translated into machine machine language | - EC
| EC2 - The holder of the degree possesses general scientific and discipline-related engineering-technical insight in the basic concepts, methods, conceptual frameworks and interdependent relations of the specific domain. | | | - DC
| EA 2.5 The student has insight into the functionality of (advanced) digital components, signals and systems. | | | | - BC
| The student understands the organization of modern computer architectures | | | | - BC
| The student understands the impact of architectural decisions on computer performance and security | - EC
| EC3 - The holder of the degree is able to recognize problems independently and can take initiative to plan activities and perform accordingly. | | | - DC
| 3.2 The student can plan a technical-scientific project in a structured manner. | | | | - BC
| The student can interpret and extend the design of a modern day microprocessor. | - EC
| EC4 - The holder of the degree can gather and obtain relevant scientific and/or technical information and/or he/she can measure the necessary information efficiently and conscientiously. Additionally, he/she can make correct references to information. | | | - DC
| 4.1 The student can look up scientific and/or technical information in a goal-oriented manner. | | | | - BC
| The student is able to acquire the necessary information for extending a computer architecture design | - EC
| EC5 - The holder of the degree can analyse unknown, domain-specific problems, subdivide them, structure them logically, determine the preconditions and interpret the data scientifically. | | | - DC
| EA-INF 5.1 The student can for a specific problem or application, analyse in which ways the software can be designed and built and can weigh alternatives based on relevant criteria. | | | | - BC
| The student can assess the performance impact of using different hardware features from software | - EC
| EC7 - The holder of the degree can use the selected methods and tools innovatively to systematically implement domain-specific solutions and designs while being aware of practical and economic conditions and company-related implications. | | | - DC
| EA-INF 7.2 The student can combine appropriate software and hardware components into a working solution. | | | | - BC
| The student knows, understands, and is able to combine and demonstrate digital hardware of processors and software running on and controlling the processor. | - EC
| EC8 - The holder of the degree can interpret (incomplete) results, can deal with uncertainties and constraints and can evaluate knowledge and skills critically to adjust own reasoning and course of action accordingly. | | | - DC
| 8.1 The student can validate (calculated, measured or simulated) results against literature and reality. | | | | - BC
| The student is able to evaluate performance and security characteristics of complex software and hardware systems | - EC
| EC9 - The holder of the degree can communicate with colleagues in oral and in written form (including in a graphical way) about domain-specific aspects in suited language making use of apt terminology. | | | - DC
| 9.1 The student is able to communicate in writing in a correct, structured and appropriate manner in languages relevant to their field of study. | | | | - BC
| The student is able to report on hardware and software design concepts using the English language. | - EC
| EC11 - The holder of the degree is able to think and act responsibly realising a project taking into account social and international values, relations and consequences. | | | - DC
| 11.2 The student has insight and takes into account the interests of different stakeholders. | | | | - BC
| The student is aware of the technological, economical and societal evolution in the area of modern processor designs and accompanying software constructs | - EC
| EC12 - The holder of the degree can act application-oriented and goal-driven and can act academically and professionally with the necessary perseverance and with eye for realism and efficiency, showing a research-oriented attitude towards lifelong learning. | | | - DC
| 12.3 The student adopts an appropriate engineering attitude (accurate, efficient, safe, result-oriented,...). | | | | - BC
| The student is able to understand a modern processor architecture, taking into account requirements for a dedicated application area, as well as practical limitation in available resources. |
|
| | EC = learning outcomes DC = partial outcomes BC = evaluation criteria |
|
|
This course assumes familiarity with computer programming (in languages such as C, Java, Python...), basic knowledge of combinatorial and sequential digital circuits, Boolean logic and introductory concepts in microcontrollers.
|
|
|
|
Introduction/refresher
- Digital hardware and CPU design concepts
CPU architecture
- Instruction set architectures
- Register file
- Memory Management Unit
- ALU (including floating point)
- Power management
- Performance monitoring
Advanced optimizations
- Pipelining
- Out-of-order execution
- Branch prediction
- Speculative execution
- Vectorization
Parallellism
- (Symmetric) Multiprocessing
- (Simultaneous) Multithreading
Memory
- Stack
- RAM and memory bus
- Cache
I/O
- Interfacing concepts
Focus in this course is the design of a RISC-V processor.
During the lab, assignments will be given to:
- understand assembly as hardware/software interface language
- understand Cadence Genus and Innovus as chip design software
- understand the complete pipelined RISC-V processor architecture, where a VHDL-based design has to be optimized for matrix multiplication.
|
|
|
|
|
|
|
|
|
Application Lecture ✔
|
|
|
|
|
|
|
|
Case study ✔
|
|
|
|
Demonstration ✔
|
|
|
|
Exercises ✔
|
|
|
|
Group work ✔
|
|
|
|
Homework ✔
|
|
|
|
Paper ✔
|
|
|
|
Presentation ✔
|
|
|
|
Report ✔
|
|
|
|
Period 1 Credits 6,00
| Evaluation method | |
|
| Practical evaluation during teaching period | 25 % |
|
| Transfer of partial marks within the academic year | ✔ |
|
|
|
|
|
|
Second examination period
| Evaluation second examination opportunity different from first examination opprt | |
|
| Explanation (English) | There is no second chance for the practical evaluation during the teaching period (project).The results from the first exam period will be transferred.
Only the written exam can be retaken.
Transfer of results of the project to next academic year if at least 12/20 has been awarded. |
|
|
|
|
|
| Recommended reading |
| |
[Computer Organization and Design],[David A. Patterson, John L. Hennessy],[RISC-V Edition],[Morgan Kaufman, Elsevier],[9780128122754],[Available as e-book: https://ebookcentral-proquest-com.bib-proxy.uhasselt.be/lib/ubhasselt/detail.action?docID=802523&pq-origsite=summon] |
|
|
| Recommended course material |
| |
All necessary additional course and reading material will be provided to the registered students. |
|
|
| Remarks |
| |
Relation with curriculum: In this course the foundations for modern computer architectures and their organization are studied, as well as getting an insight in the reasons and motivations for their current organization. This insight and practical experience allows to make appropriate choises in research to be able to select the appropiate architectures to solve specific problems. At regular instances during the course, links to scientific research and industrial evolutions are provided. This course lays the basics for several advanced courses in the Master, where concepts introduced here will be practically used and/or implemented.
Relation with the work field: computers form the basis of current electronics ICT. A good knowledge of the fundamentals of their architectures and organization are valuable in the professional carreers of electronics ICT engineers.
Relation to research: this course builds on research on digital hardware software systems, FPGA's, complex hardware systems architectures. |
|
|
|
|
|
| Bridging programme Electronics and ICT Engineering Technology - part 1 | Compulsory | 162 | 6,0 | 162 | 6,0 | Yes | Yes | Numerical | |
|
| |
|
|
This course assumes familiarity with computer programming (in languages such as C, Java, Python...), basic knowledge of combinatorial and sequential digital circuits, Boolean logic and introductory concepts in microcontrollers.
|
|
|
|
Introduction/refresher
- Digital hardware and CPU design concepts
CPU architecture
- Instruction set architectures
- Register file
- Memory Management Unit
- ALU (including floating point)
- Power management
- Performance monitoring
Advanced optimizations
- Pipelining
- Out-of-order execution
- Branch prediction
- Speculative execution
- Vectorization
Parallellism
- (Symmetric) Multiprocessing
- (Simultaneous) Multithreading
Memory
- Stack
- RAM and memory bus
- Cache
I/O
- Interfacing concepts
Focus in this course is the design of a RISC-V processor.
During the lab, assignments will be given to:
- understand assembly as hardware/software interface language
- understand Cadence Genus and Innovus as chip design software
- understand the complete pipelined RISC-V processor architecture, where a VHDL-based design has to be optimized for matrix multiplication.
|
|
|
|
|
|
|
|
|
Application Lecture ✔
|
|
|
|
|
|
|
|
Case study ✔
|
|
|
|
Demonstration ✔
|
|
|
|
Exercises ✔
|
|
|
|
Group work ✔
|
|
|
|
Homework ✔
|
|
|
|
Paper ✔
|
|
|
|
Presentation ✔
|
|
|
|
Report ✔
|
|
|
|
Period 1 Credits 6,00
| Evaluation method | |
|
| Practical evaluation during teaching period | 25 % |
|
| Transfer of partial marks within the academic year | ✔ |
|
|
|
|
|
|
Second examination period
| Evaluation second examination opportunity different from first examination opprt | |
|
| Explanation (English) | There is no second chance for the practical evaluation during the teaching period (project).The results from the first exam period will be transferred.
Only the written exam can be retaken.
Transfer of results of the project to next academic year if at least 12/20 has been awarded. |
|
|
|
|
|
| Recommended reading |
| |
[Computer Organization and Design],[David A. Patterson, John L. Hennessy],[RISC-V Edition],[Morgan Kaufman, Elsevier],[9780128122754],[Available as e-book: https://ebookcentral-proquest-com.bib-proxy.uhasselt.be/lib/ubhasselt/detail.action?docID=802523&pq-origsite=summon] |
|
|
| Recommended course material |
| |
All necessary additional course and reading material will be provided to the registered students. |
|
|
| Remarks |
| |
Relation with curriculum: In this course the foundations for modern computer architectures and their organization are studied, as well as getting an insight in the reasons and motivations for their current organization. This insight and practical experience allows to make appropriate choises in research to be able to select the appropiate architectures to solve specific problems. At regular instances during the course, links to scientific research and industrial evolutions are provided. This course lays the basics for several advanced courses in the Master, where concepts introduced here will be practically used and/or implemented.
Relation with the work field: computers form the basis of current electronics ICT. A good knowledge of the fundamentals of their architectures and organization are valuable in the professional carreers of electronics ICT engineers.
Relation to research: this course builds on research on digital hardware software systems, FPGA's, complex hardware systems architectures. |
|
|
|
|
|
| Exchange Programme Engineering Technology | Optional | 162 | 6,0 | 162 | 6,0 | Yes | Yes | Numerical | |
|
| |
|
|
Introduction/refresher
- Digital hardware and CPU design concepts
CPU architecture
- Instruction set architectures
- Register file
- Memory Management Unit
- ALU (including floating point)
- Power management
- Performance monitoring
Advanced optimizations
- Pipelining
- Out-of-order execution
- Branch prediction
- Speculative execution
- Vectorization
Parallellism
- (Symmetric) Multiprocessing
- (Simultaneous) Multithreading
Memory
- Stack
- RAM and memory bus
- Cache
I/O
- Interfacing concepts
Focus in this course is the design of a RISC-V processor.
During the lab, assignments will be given to:
- understand assembly as hardware/software interface language
- understand Cadence Genus and Innovus as chip design software
- understand the complete pipelined RISC-V processor architecture, where a VHDL-based design has to be optimized for matrix multiplication.
|
|
|
|
|
|
|
|
|
Application Lecture ✔
|
|
|
|
|
|
|
|
Case study ✔
|
|
|
|
Demonstration ✔
|
|
|
|
Exercises ✔
|
|
|
|
Group work ✔
|
|
|
|
Homework ✔
|
|
|
|
Paper ✔
|
|
|
|
Presentation ✔
|
|
|
|
Report ✔
|
|
|
|
Period 1 Credits 6,00
| Evaluation method | |
|
| Practical evaluation during teaching period | 25 % |
|
| Transfer of partial marks within the academic year | ✔ |
|
|
|
|
|
|
Second examination period
| Evaluation second examination opportunity different from first examination opprt | |
|
| Explanation (English) | There is no second chance for the practical evaluation during the teaching period (project).The results from the first exam period will be transferred.
Only the written exam can be retaken.
Transfer of results of the project to next academic year if at least 12/20 has been awarded. |
|
|
|
|
|
| Recommended reading |
| |
[Computer Organization and Design],[David A. Patterson, John L. Hennessy],[RISC-V Edition],[Morgan Kaufman, Elsevier],[9780128122754],[Available as e-book: https://ebookcentral-proquest-com.bib-proxy.uhasselt.be/lib/ubhasselt/detail.action?docID=802523&pq-origsite=summon] |
|
|
| Recommended course material |
| |
All necessary additional course and reading material will be provided to the registered students. |
|
|
| Remarks |
| |
Relation with curriculum: In this course the foundations for modern computer architectures and their organization are studied, as well as getting an insight in the reasons and motivations for their current organization. This insight and practical experience allows to make appropriate choises in research to be able to select the appropiate architectures to solve specific problems. At regular instances during the course, links to scientific research and industrial evolutions are provided. This course lays the basics for several advanced courses in the Master, where concepts introduced here will be practically used and/or implemented.
Relation with the work field: computers form the basis of current electronics ICT. A good knowledge of the fundamentals of their architectures and organization are valuable in the professional carreers of electronics ICT engineers.
Relation to research: this course builds on research on digital hardware software systems, FPGA's, complex hardware systems architectures. |
|
|
|
|
|
1 Education, Examination and Legal Position Regulations art.12.2, section 2. |
| 2 Education, Examination and Legal Position Regulations art.16.9, section 2. |
3 Education, Examination and Legal Position Regulations art.15.1, section 3.
|
| Legend |
| SBU : course load | SP : ECTS | N : Dutch | E : English |
|