| Language of instruction : English |
| Exam contract: not possible |
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Sequentiality
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No sequentiality
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| Degree programme | | Study hours | Credits | P1 SBU | P1 SP | 2nd Chance Exam1 | Tolerance2 | Final grade3 | |
 | Master of Electronics and ICT Engineering Technology | Optional | 108 | 4,0 | 108 | 4,0 | Yes | Yes | Numerical |  |
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| | | Learning outcomes |
- EC
| EC1 - The holder of the degree thinks and acts professionally with an appropriate engineering attitude and continuous focus on personal development, adequately communicates, effectively cooperates, takes into account the economical, ethical, social and/or international context and is hereby aware of the impact on the environment. | | | - DC
| DC-M8 - can evaluate knowledge and skills critically to adjust own reasoning and course of action accordingly. | | | | - BC
| The students can debug the designed subcomponents in the project and adapt them to obtain a working solution. | | | | - BC
| The students can debug the designed interfaces between the subcomponents in the project and adapt them to obtain a working solution. | | | - DC
| DC-M10 - can function constructively and responsibly as member of a (multidisciplinary) team. | | | | - BC
| The students can divide their project into subcomponents that will be designed separately. | | | | - BC
| The students can combine the subcomponents in the project in discussion with each other in order to obtain a working solution. | | | - DC
| DC-M12 - shows a suitable engineering attitude. | | | | - BC
| The students can correctly interpret, process and benchmark the experimental results of the project in an independent and correct way. | | | | - BC
| The students can optimize the digital system designed in the project towards small area or high speed. | - EC
| EC5 - The holder of the degree has specialist knowledge of and insight in principles and applications within the domains of digital electronics, in which he/she can independently initiate, plan, critically analyse and create solid solutions with eye for data processing and implementation, with the help of simulation techniques or advanced tools, while being aware of potential mistakes, practical constraints and with attention to the topical technological developments. | | | - DC
| DC-M1 - has knowledge of the basic concepts, structures and coherence. | | | | - BC
| The students can explain the treated concepts related to CMOS testing. | | | | - BC
| The students can explain the treated concepts related to low-power digital design. | | | - DC
| DC-M2 - has insight in the basic concepts and methods. | | | | - BC
| The students can apply the treated concepts related to CMOS testing in dedicated exercises. | | | | - BC
| The students can apply the treated concepts related to low-power design in dedicated exercises. | | | - DC
| DC-M5 - can analyze problems, logically structure and interpret them. | | | | - BC
| The students can apply the treated concepts related to CMOS testing to analyze a given test method. | | | | - BC
| The students can apply the treated concepts related to CMOS testing to analyze a given digital circuit. | | | - DC
| DC-M7 - can use selected methods and tools to implement solutions and designs. | | | | - BC
| The students can apply the treated concepts related to CMOS testing to design and implement a test strategy for a given digital circuit. | | | | - BC
| The students can apply the treated concepts related to low-power digital design to design and implement a digital circuit. | | | | - BC
| The students can apply hardware verification techniques to a digital design | - EC
| EC6 - The holder of the degree has specialist knowledge of and insight in principles and applications within the domains of analogue electronics, in which he/she can independently initiate, plan, critically analyse and create solid solutions with eye for data processing and implementation, with the help of simulation techniques or advanced tools, while being aware of potential mistakes, practical constraints and with attention to the topical technological developments. | | | - DC
| DC-M1 - has knowledge of the basic concepts, structures and coherence. | | | | - BC
| The students can explain the treated concepts related to semiconductor memories. | | | | - BC
| The students can explain the treated concepts related to flipflops and latches. | | | - DC
| DC-M2 - has insight in the basic concepts and methods. | | | | - BC
| The students can apply the treated concepts related to semiconductor memories in dedicated exercises. | | | | - BC
| The students can apply the treated concepts related to flipflops and latches in dedicated exercises. | | | - DC
| DC-M5 - can analyze problems, logically structure and interpret them. | | | | - BC
| The students can apply the treated concepts related to semiconductor memories to analyze a given circuit. | | | | - BC
| The students can apply the treated concepts related to flipflops and latches to analyze a given circuit. | | | - DC
| DC-M6 - can select methods and make calculated choices to solve problems or design solutions. | | | | - BC
| The students can apply the treated concepts related to semiconductor memories to design a circuit. | | | | - BC
| The students can apply the treated concepts related to flipflops and latches to design a circuit. |
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| | EC = learning outcomes DC = partial outcomes BC = evaluation criteria |
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Application lecture:
CMOS test methods
Semiconductor memories
D-flip-flops and latches
Design techniques for low-power digital systems
Project:
Independent assignment: hardware verification of a digital design
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Application Lecture ✔
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Project ✔
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Exercises ✔
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Report ✔
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Seminar ✔
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Period 1 Credits 4,00
| Evaluation method | |
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| Practical evaluation during teaching period | 50 % |
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| Transfer of partial marks within the academic year | ✔ |
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Second examination period
| Evaluation second examination opportunity different from first examination opprt | |
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| Explanation (English) | There is no second exam chance for the project. The mark from the first exam period is transferred to the second exam period.
The mark of the project can be transferred to the next academic year if the mark is at least 12/20. |
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| Compulsory course material |
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Slides and exercises of the application lectures shared in Toledo |
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| Exchange Programme Engineering Technology | Optional | 108 | 4,0 | 108 | 4,0 | Yes | Yes | Numerical | |
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|
Application lecture:
CMOS test methods
Semiconductor memories
D-flip-flops and latches
Design techniques for low-power digital systems
Project:
Independent assignment: hardware verification of a digital design
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|
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Application Lecture ✔
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Project ✔
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Exercises ✔
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Report ✔
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Seminar ✔
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Period 1 Credits 4,00
| Evaluation method | |
|
| Practical evaluation during teaching period | 50 % |
|
| Transfer of partial marks within the academic year | ✔ |
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|
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Second examination period
| Evaluation second examination opportunity different from first examination opprt | |
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| Explanation (English) | There is no second exam chance for the project. The mark from the first exam period is transferred to the second exam period.
The mark of the project can be transferred to the next academic year if the mark is at least 12/20. |
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| Compulsory course material |
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Slides and exercises of the application lectures shared in Toledo |
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1 examination regulations art.1.3, section 4. |
| 2 examination regulations art.4.7, section 2. |
3 examination regulations art.2.2, section 3.
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| Legend |
| SBU : course load | SP : ECTS | N : Dutch | E : English |
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